1. Field of the Invention
The present invention relates to an electrostatic discharge protection (ESD) device, and in particular, to an electrostatic discharge protection (ESD) device coupled between two circuits.
2. Description of the Related Art
Semiconductor devices, may suffer from electrostatic discharge (ESD) damage when being fabricated, assembled, delivered, tested or applied. Thus, ESD protection is required for semiconductor devices to prevent against ESD damage and insure quality thereof.
FIG. 1a is a schematic view of a conventional power cut cell 50 coupled between two circuits 20a and 20b. The conventional power cut cell 50 is constructed by a diode series module 52 and a reverse diode series module 54 in parallel connection. The diode series module 52 is constructed by two diodes 52a in series connection and the diode series module 54 is constructed by two diodes 54a in series connection. The conventional power cut cell 50 coupled between a voltage power supply terminal VCC1/ground terminal GND1 of the circuit 20a and a voltage power supply terminal VCC2/ground terminal GND2 of the circuit 20b has an ESD path therebetween. For example, if the voltage power supply terminal VCC1/ground terminal GND1 of the circuit 20a encounters ESD current zapping, the diode series module 52 of the conventional power cut cell 50 in a forward-bias operation would thereby turn on the conventional power cut cell 50. Thus, the conventional power cut cell 50 would transmit the ESD transient current to the corresponding voltage power supply terminal VCC2/ground terminal GND2 of the circuit 20b. Alternatively, if the voltage power supply terminal VCC2/ground terminal GND2 of the circuit 20b encounters ESD current zapping, the diode series module 52 of the conventional power cut cell 50 in a forward-bias operation would thereby turn off the conventional power cut cell 50. The conventional power cut cell 50 would transmit the ESD transient current to the corresponding voltage power supply terminal VCC1/ground terminal GND1 of the circuit 20a, thereby preventing a secured device 10a in the circuit 20a or a secured device 10b in the circuit 20b from ESD damage. Additionally, the conventional power cut cell 50 constructed by diodes may be designed with noise isolation for the circuit 20a or 20b when the conventional power cut cell 50 is turned off.
FIG. 1b is an equivalent circuit diagram of the conventional power cut cell 50 as shown in FIG. 1a. A parasitic resistance is formed between the N-well or P-well regions because the conventional power cut cell 50 is constructed by a PN diode formed by N-wells or P-wells. As shown in FIG. 1b, an equivalent circuit of the diodes 52a of the diode series module 52 can serve as an ideal diode 52a1 with zero impedance, which is series connected to a parasitic resistance 52a2. The parasitic resistance, however, hinders transmission of the ESD transient current. While the well area can be increased to reduce the parasitic resistance of the conventional power cut cell 50, total device area would increase and thereby counter the desired trends for high device density.
FIG. 2 is a schematic view of another conventional power cut cell 30. To reduce the parasitic resistance of the power cut cell, a power cut cell 30 comprising of a metal-oxide-silicon (MOS) transistor 32 and a reverse MOS transistor 34 in parallel connection can be used. When an ESD transient current is larger than a threshold voltage of the MOS transistor, the MOS transistors 32 and 34 are turned on, thereby transmitting the ESD transient current from the voltage power supply terminal VCC1/ground terminal GND1 of one circuit to a corresponding voltage power supply terminal VCC2/ground terminal GND2 of another circuit. The power cut cell 30 can transmit the larger ESD transient current because the output impedance of the MOS transistors 32 and 34 that are turned on is much smaller than the parasitic resistances 52a2 or 54a2 of the conventional power cut cell 50 constructed by diodes. Additionally, the threshold voltage of the MOS transistors 32 and 34 helps to isolate noise from adjacent circuits. Thus, the ESD transient current is transmitted by reducing the output impedance of the power cut cell 30. However, like the conventional power cut cell 50 as shown in FIG. 1a, total device area is large, thereby countering the desired trends for high device density.
Thus, a high device density ESD protection device, which has low parasitic resistance when the ESD protection device is turned on and has good noise isolation when the ESD protection device is turned off, is desired.